tecnología cmos: avances y perspectivas cmos

Andrea G. Martínez-López, Edgar Solís-Ávila, Jaime Martínez-Castillo, Julio C. Tinoco Magaña


La electrónica moderna, conocida como microelectrónica, ha evolucionado de manera notable en las últimas décadas gracias a diversos progresos científicos y tecnológicos. Durante los primeros años de la década de 1960, se desarrollaron los transistores de efecto de campo Metal-Óxido-Semiconductor y con ellos la tecnología Metal-Óxido-Semiconductor Complementaria, lo cual dio un impulso sin precedentes a la microelectrónica. Desde aquellos años, el avance observado ha sido guiado por la continua reducción de las dimensiones de los transistores utilizados en la fabricación de los circuitos integrados, llegando a tecnologías actuales cuyas dimensiones son del orden de decenas de nanómetros. A medida que se reducen las dimensiones de los transistores, comienzan a aparecer un conjunto de fenómenos que degradan su funcionamiento. Por ello, la tecnología ha buscado diferentes alternativas a fin de continuar con el progreso observado. En este contexto, los transistores de efecto de campo de múltiples compuertas aparecen como una alternativa viable para guiar a la tecnología hacia los dispositivos de menos de 10 nm (sub-10 nm).

Palabras clave

MOSFET; MOSFET avanzados; FinFET; CMOS; circuitos integrados

Texto completo:



Abbasi, S. A. y Brunnschweiler, A. (1981). Effects of masking oxide on diffusion into silicon. IEE Proceedings-I: Solid State and Electron Devices. 128(5), 185-188.

Atalla, M.M., Tannenbaum, E. y Scheibner, E. J. (1959). Stabilization of silicon surfaces by thermally grown oxides. The Bell System Technical Journal. 38(3), 749-783.

An, T.Y., Choe, K.-K., Kwon, K.-W., Kim S.Y. (2014). Performance Optimization Study of FinFETs Considering Parasitic Capacitance and Resistance. Journal of Semiconductor Technology and Science. 14(5), 525,536.

Baccarani, G., Wordeman, M. R. y Dennard, R. H. (1984). Generalized scaling theory and its application to a ¼ micrometer MOSFET design. IEEE Transactions on Electron Devices, 31(4), 452-462.

Bhole, M., Kurude, A. y Pawar, S. (2013). FinFET- Benefits, Drawbacks and Challenges. International Journal of Engineering Sciences & Research Technology, 2(11), 3219-3222.

Bondyopadhyay, P. K. (1998). W=Shockley, the transistor pioneer-portrait of an inventive genius. Proceedings of the IEEE, 86(1), 191-217.

Borah, M., Owens, R. M. and Irwin, M. J. (1996). Transistor sizing for low power CMOS circuits. IEEE Transactions on Computer-aided Design of Integrated Circuits Systems, 15(6), 665-671.

Chang-Liao, K.-S. y Chen, L.-C. (1997) Physical and electrical properties in metal-oxide-Si capacitors with various gate electrodes and gate oxides. Journal of Vacuum Science & Technology B, 15, 942-947.

Chatterjee, P. K., Hunter, W. R., Holloway, T. C. y Lin, Y. T. (1980) The impact of scaling laws on the choice of n-channel or p-channel for MOS VLSI. IEEE Electron Device Letters, 1(10), 220-223.

Chau, R., Datta, S., Doczy, M., Doyle, B., Jin, B., Kavalieros, J., Majumdar, A., Metz, M. y Radosavljevic, M. (2005) Benchmarking nanotechnology for high-performance and low-power logic transistor applications. IEEE Transactions on Nanotechnology, 4(2), 153-158.

Chaudhry, A. y Kumar, M. J. (2004) Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review. IEEE Transactions on Device Materials Reliability, 4(1), 99-109.

Chen, C.-E. D., Matloubian, M., Sundaresan, R., Mao, B., Wei, C.C. y Pollack, G.P. (1988) Single-transistor latch in SOI MOSFET. IEEE Electron Device Letters, 9(12), 636-638.

Chern, J. G. J., Chang, P., Motta, R. F. and Godinho, N. (1980). A new method to determine MOSFET channel length. IEEE Electron Device Letters, 1(9), 170-173.

Choi, J. H., Mao, Y., Chang, J. P. (2011). Development of hafnium based high-k materials—A review. Materials Science and Engineering R 72, 97–136.

Choi, Y.-K., Chang, L., Ranade, P., Lee, J.-S, Ha, D., Balasubramanian, S., Agarwal, A., Ameen, M., King, T.-J y Bokor, J. (2002). FinFET process refinements for improved mobility and gate work function engineering. International Electron Devices Meeting, San Francisco, CA, 259-262.

Chuang, C.-T., Lu, P.-F y Anderson, C. J. (1998). SOI for digital CMOS VLSI: design considerations and advances. Proceedings of the IEEE, 86(4), 689-720.

Clemens, J. T. (1997) Silicon microelectronics technology. Bell Labs Technical Journal, 2(4), 76-102.

Colinge, J.-P. (2004) Multiple-gate SOI MOSFETs. Solid-State Electronics, 48(6), 897-905.

Colinge, J. P. (2004). Silicon-on-Insulator Technology: Materials to VLSI. NY: Springer.

Colinge, J.-P. (2008). FinFETs and Other Multi-Gate Transistors. Springer: Cambridge.

Colinge, J.-P, Baie, X. y Bayot, V. (1994) Evidence of two-dimensional carrier confinement in thin n-channel SOI gate-all-around (GAA) devices. IEEE Electron Device Letters, 15(6), 193-195.

Crupi, G., Schreurs D. M.M.-P., Raskin J.-P. y Caddemi A. (2013). A comprehensive review on microwave FinFET modeling for progressing beyond the state of art. Solid-State Electronics, 80, 81-95.

Dallmann, D. A. y Shenai, K. (1995). Scaling constraints imposed by self-heating in submicron SOI MOSFET's. IEEE Transactions on Electron Devices, 42(3), 489-496.

Davari, B., Dennard, R. H. y Shahidi, G. G. (1995). CMOS scaling for high performance and low power-the next ten years. Proceedings of the IEEE, 83(4), 595-606.

Dennard, R. H., Gaensslen, F. H., Yu, H.-N., Rideout, V. L., Bassous, E. y Leblanc, A. R. (1974). Design of ion-implanted MOSFET's with very small physical dimensions. IEEE Journal of Solid-State Circuits, 9(5), 256-268.

Elthakeb, A.T., Abd Elhamid, H., Ismail, Y. (2013). Scaling of TG-FinFETs: 3-D Monte Carlo Simulations in the Ballistic and Quasi-Ballistic Regimes. IEEE Transactions on Electron Devices, 62(6), 1796-1802.

Enz, C. (2002). An MOS transistor model for RF IC design valid in all regions of operation. IEEE Transactions on Microwave Theory and Techniques. 50(1), 342-359.

Ernst, T., Tinella, C., Raynaud, C. y Cristoloveanu, S. (2002). Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: optimization of the device architecture. Solid-State Electronics, 46(3), 373-378.

Ferlet-Cavrois, V., Gasiot, G., Marcandella, C., D'Hose, C., Flament, O., Faynot, O., du Port de Pontcharra, J. y Raynaud, C. (2002). Insights on the transient response of fully and partially depleted SOI technologies under heavy-ion and dose-rate irradiations. IEEE Transactions on Nuclear Science, 49(6), 2948-2956.

Gang, H., Zhaoqi S., Guang, L., Lide Z. (2012). Review and Perspective of Hf-based High-k Gate Dielectrics on Silicon. Critical Reviews in Solid State and Materials Sciences, 37, 131–157.

Garrett, L. S. (1970). Integrated-circuit digital logic families III -ECL and MOS devices. IEEE Spectrum, 7(12), 30-42.

Gregory, B. L. y Shafer, B. D. (1973). Latch-Up in CMOS Integrated Circuits. IEEE Transactions on Nuclear Science, 20(6) 293-299.

Grove, A. S. (1967). Physics and technology of semiconductor devices. John Wiley: NY.

Grove, A. S., Leistiko, O. Jr. y Hooper, W. W. (1967). Effect of surface fields on the breakdown voltage of planar silicon p-n junctions. IEEE Transactions on Electron Devices, 14(3), 157-162.

Hiroki, A., Yamate, A. y Yamada, M. (2008). An analytical MOSFET model including gate voltage dependence of channel length modulation parameter for 20nm CMOS. International Conference on Electrical and Computer Engineering, Dhaka, 139-143.

Hisamoto, D., Kaga, T., Kawamoto, Y. y Takeda, E. (1989). A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET. International Electron Device Meeting, Washington DC, 833-836.

Hofstein, S. R. y Heiman F. P. (1963). The silicon insulated-gate field-effect transistor. Proceedings of the IEEE, 51(9), 1190-1202.

Howes, R., Redman-White, W., Nichols, K.G., Mole, P. J., Robinson, M. J. y Bird, S. (1994). An SOS MOSFET model based on calculation of the surface potential. IEEE Transactions on Computer-aided Design of Integrated Circuits Systems, 13(4), 494-506.

Hsu, S. T. (1978). Electron mobility in SOS films. IEEE Transactions on Electron Devices, 25(8), 913-916.

ITRS (2013). International Technology Roadmap for Semiconductors. Recuperado de http://www.itrs.net/.

Itoh, K. (2013). A Historical Review of Low-Power, Low-Voltage Digital MOS Circuits Development. IEEE Solid-State Circuits Magazine, 5(1), 27-39.

Iwai, H. (2009). Roadmap for 22 nm and beyond. Microelectronic Engineering 86(6-7), 1520–1528.

Iwai, H. y Ohmi, S. (2002). Silicon integrated circuit technology from past to future. Microelectronics Reliability, 42(4-5), 465-491.

Kahng, D. (1976). A historical perspective on the development of MOS transistors and related devices. IEEE Transactions on Electron Devices, 23(7), 655-657.

Kahng, D. y Atalla, M. M. (1960). Silicon-silicon dioxide field induced surface devices. IRE-AIEE Solid-State Device Research Conference, Pittsburgh, PA.

Kang, S. M. (1986). Accurate simulation of power dissipation in VLSI circuits. IEEE Journal Solid-State Circuits, 21(5), 889-891.

Kilby, J. S. (1964). Miniaturized electronic circuits. U.S. Patent 3 138 743.

Kilby, J. S. (1976). Invention of the integrated circuit. IEEE Transactions on Electron Devices, 23(7), 648-654.

Kim, D., Kang, Y., Ryu, M., y Kim, Y. (2013). Simple and Accurate Capacitance Modeling of 32nm Multi-fin FinFET. IEEE Proc. of the International SoC Design Conference (ISOCC), Busan, Korea, 392-393.

Lee, C.-W., Yun, S.-R.-N., Park, J.-T y Colinge, J.-P. (2007). Device design guidelines for nano-scale MuGFETs. Solid-State Electronics, 51(3), 505.

Lilienfeld, J. E. (1930). Method and apparatus for controlling electric currents. U.S. Patent 1 745 175.

Lilienfeld, J. E. (1932). Amplifier for electric currents. U.S. Patent 1 877 140.

Lilienfeld, J. E. (1933). Device for controlling electric current. U.S. Patent 1 900 018.

Lima, L. P. B., Moreira, M. A., Diniz, J. A., y Doi, I. (2012). Titanium nitride as promising gate electrode for MOS technology. Phys. Status Solidi C. 9, 1427–1430.

Łukasiak , L. y Jakubowski. A. (2010). History of semiconductors. Journal of Telecommunications and Information Technology, 1, 3-9.

Mayer, D. C., Cole, R. C. y Pollack, G. P. (1991). Determination of back interface state distribution in fully depleted SOI MOSFET. International Electron Device Meeting, Washington, DC, 329-332.

Mead, C. A. (1994). Scaling of MOS technology to submicrometer feature sizes. Analog Integrated Circuits and Signal Process. 6(1), 9-25.

Mishra, P., Muttreja, A., y Jha, N. K. (2011). Finfet circuit design. In Nanoelectronic Circuit Design, pp. 23-54. Springer: NY.

Noyce, R. N. (1961). Semiconductor device and lead structure. U.S. Patent 2 981 877.

Noyce, R. N. (1968). Making integrated electronics technology work. IEEE Spectrum, 5(5), 63-66.

Ochoa, A., Dawes, W. y Estreich, D. (1979). Latch-Up Control in CMOS Integrated Circuits. IEEE Transactions on Nuclear Science, 26(6), 5065-5068.

Pae, S., Prasad, C., Ramey, S., Thomas, J., Rahman, A., Lu, R., Hicks, J., Batzer, S., Zhao, Q., Hatfield, J., Liu. M., Parker, C., y Woolery, B. (2012). Gate Dielectric TDDB Characterizations of Advanced High-K and Metal-Gate CMOS Logic Transistor Technology. Reliability Physics Symposium, Anaheim, CA, 5C.1.1-5C.1.5.

Pereira, A.S.N., Giacomini, R., (2015). An accurate closed-expression model for FinFETs parasitic resistance. Microelectronics Reliability. 55, 470–480.

Pfiester, J. R., Shott, J.D. y Meindl, J. D. (1985). Performance limits of CMOS ULSI. IEEE Transactions on Electron Devices, 32(2), 333-343.

Poiroux, T., Vinet, M., Faynot, O., Widiez, J., Lolivier J., Ernst, T. Previtali, B. y Deleonibus, S. (2005). Microelectronic Engineering, 80, 378-385.

Pucel, R. A. (1981). Design Considerations for Monolithic Microwave Circuits. IEEE Transactions on Microwave Theory and Techniques, 59(6), 513-534.

Ragnarsson, L.-Å., Chiarella, T., Togo, M., Schram, T., Absil, P., Hoffmann, T. (2011). Ultrathin EOT high-κ/metal gate devices for future technologies: Challenges, achievements and perspectives. Microelectronic Engineering, 88(7), 1317–1322.

Raj, B. (2013). Quantum Mechanical Potential Modeling of FinFET. In Toward Quantum FinFET (pp. 81-97). Springer International Publishing.

Rogenmoser, R. y Kaeslin, H. (1997). The impact of transistor sizing on power efficiency in submicron CMOS circuits. IEEE Journal of Solid-State Circuits, 32(7), 1142-1145.

Roy, K., Mukhopadhyay, S. y Mahmoodi-Meimand, S. H. (2003). Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proceedings of the IEEE, 91(2), 305-327.

Sah, R. L-Y. (1988). Evolution of the MOS transistor-from conception to VLSI. Proceedings of the IEEE, 76(10), 1280-1326.

Sah, R.L-Y. (1988). Evolution of the MOS transistor-from conception to VLSI. Proceedings of the IEEE, 76(10), 1280-1326.

Saha, S. (2001). Design considerations for 25 nm MOSFET devices. Solid-State Electronics, 45(10), 1851-1857.

Schmitz, A. E., Walden, R. H., Larson, L. E., Rosenbaum, S. E., Metzger, R. A., Behnke, J. R. y Macdonald, P. A. (1991). A deep-submicrometer microwave/digital CMOS/SOS technology. IEEE Electron Device Letters, 12(1), 16-17.

Schwank, J. R. (2003). Radiation effects in SOI technologies. IEEE Transactions on Nuclear Science, 50(3), 522-538.

Sekigawa, T. y Hayashi, Y. (1984). Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate. Solid-State Electronics, 27(8-9), 827-828.

Seong-Dong, K., Cheol-Min, P. y Woo, J. C. S. (2002). Advanced model and analysis of series resistance for CMOS scaling into nanometer regime. I. Theoretical derivation. IEEE Transactions on Electron Devices, 49(3), 457-466.

Shahidi, G. G., Ning, T. H., Chappell, T. I., Comfort, J. H., Chappell, B. A., Franch, R., Anderson, C. J., Cook, P. W., Schuster, S. E., Rosenfield, M. G., Polcari, M. R., Dennard, R. H. y Davari, B. (1993). SOI for a 1-volt CMOS technology and application to a 512 Kb SRAM with 3.5 ns access time. International Electron Device Meeting, Washington DC, 813-816.

Shockley, W. (1976). The path to the conception of the junction transistor. IEEE Transactions on Electron Devices, 23(7), 597-620.

Subramanian, V., Parvais, B., Borremans, J., Mercha, A., Linten, D., Wambacq, P., Loo, J., Dehan, M., Gustin, C., Collaert, N., Kubicek, S., Lander, R., Hooker, J., Cubaynes, F., Donnay, S., Jurczak, M., Groeseneken, G., Sansen, Willy y Decoutere, S. (2006). Planar Bulk MOSFETs Versus FinFET: An Analog/RF Perspective. IEEE Transactions on Electron Devices, 53(12), 3071-3079.

Suzuki, E., Ishii, K., Kanemaru, S., Maeda, T., Tsutsumi, T., Sekigawa, T., Nagai, K. y Hiroshima, H. (2000). Highly suppressed short-channel effects in ultrathin SOI n-MOSFETs. IEEE Transactions on Electron Devices, 47(2), 354-359.

Suzuki, V., Odagawa, K. y Abe, T. (1973). Clocked CMOS calculator circuitry. IEEE Journal Solid-State Circuit, 8(6), 462-469.

Sze, S. M. (1985). Physics of Semiconductor Devices. Wiley: NY.

Takagi, S., Toriumi, A., Iwase, M. y Tango, H. (1994). On the universality of inversion layer mobility in Si MOSFET: Part I-effects of substrate impurity concentration. IEEE Transactions on Electron Devices, 41(12), 2357-2362.

Tenbroek, B. M., Lee, M. S. L., Redman-White, W., Bunyan, R. J. T., y Uren, M.J. (1996). Self-heating effects in SOI MOSFETs and their measurement by small signal conductance techniques. IEEE Transactions on Electron Devices, 43(12), 2240-2248.

Uyemura, J. P. (2001). CMOS logic circuit design, Springer.

Veendrick, H. J. M. (1984). Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits. IEEE Journal of Solid-State Circuits, 19(4), 468-473.

Wallmark, J. T. (1959). Field-Effect Transistor, U.S. Patent 2 900 531.

Wang, P. P. (1978). Device characteristics of short-channel and narrow-width MOSFET's. IEEE Transactions on Electron Devices, 25(7), 779-786.

Wang, Q.-Y, Nie, J.-P., Yu, F., Liu, Z.-L., y Yu, Y.-H. (2000). Improvement of thin silicon on sapphire (SOS) film materials and device performances by solid phase epitaxy. Materials Science Engineering: B, 72(2-3), 189-192.

Wang, X., Brown, A.R., Binjie Cheng, Asenov, A. (2011). Statistical variability and reliability in nanoscale FinFETs. International Electron Devices Meeting, Washington DC, 5.4.1-5.4.4.

Wanlass, F. M. y Sah, C. T. (1963). Nanowatt logic using field-effect metal-oxide semiconductor triodes. ISSCC digest of technical papers, IV, Philadelphia, PA, 32-33.

Wei, A., Sherony, M. J. y Antoniadis, D. A. (1995). Transient behavior of the kink effect in partially-depleted SOI MOSFET's. IEEE Electron Device Letters, 16(11), 494-496.

Weize, X., Gebara, G., Zaman, J., Gostkowski, M., Nguyen, B., Smith, G., Lewis, D., Cleavelin, C.R., Wise, R., Yu, S., Pas, M., King, T.-J. y Colinge, J.P. (2004). Improvement of FinFET electrical characteristics by hydrogen annealing. IEEE Electron Device Letters, 25(8), 541-543.

Wong, H. e Iwai, H. (2006). On the scaling issues and high-κ replacement of ultrathin gate dielectrics for nanoscale MOS transistors. Microelectronic Engineering, 83(10), 1867-1904.

Yamaguchi, K. (1983). A mobility model for carriers in the MOS inversion layer. IEEE Transactions on Electron Devices, 30, 658-663.

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